Verilog Projects (updated 2025-03-13)

I2C Bus Tutorial [upl. by Oderfliw65]

I2C Bus Tutorial

Duration: 17:28
100.2K views | May 4, 2011

FPGA Tutorial Image Processing in Verilog [upl. by Luiza]

FPGA Tutorial Image Processing in Verilog

Duration: 15:39
56.3K views | Aug 20, 2018

Whats an FPGA [upl. by Dragon]

Duration: 1:26
211.2K views | Jul 8, 2019

Image processing on FPGA using Verilog HDL [upl. by Kaela]

Image processing on FPGA using Verilog HDL

Duration: 22:49
24.8K views | Feb 25, 2021

Writing a Verilog Testbench [upl. by Nirrek88]

Writing a Verilog Testbench

Duration: 9:15
94.7K views | Aug 28, 2017

System Design Through VERILOG Intro Video [upl. by Renaud]

System Design Through VERILOG Intro Video

Duration: 5:35
87K views | May 13, 2021

Lesson 1 Basic Logic Gates [upl. by Ylsew]

Lesson 1 Basic Logic Gates

Duration: 10:50
535.5K views | Oct 22, 2012

Verilog Tutorial Introduction to Verilog [upl. by Elgar213]

Verilog Tutorial Introduction to Verilog

Duration: 9:27
153.5K views | Aug 14, 2017

19 Describing Multiplexers in Verilog [upl. by Crane]

19 Describing Multiplexers in Verilog

Duration: 30:35
10.2K views | Feb 15, 2021

VERILOG HDL Data Flow Modelling Examples [upl. by Leiuqese]

VERILOG HDL Data Flow Modelling Examples

Duration: 11:55
24.2K views | Jan 14, 2021

VERILOG MODELING OF THE PROCESSOR PART 1 [upl. by Henn722]

VERILOG MODELING OF THE PROCESSOR PART 1

Duration: 30:03
35.8K views | Sep 21, 2017

System Verilog Tutorial 1 Randomization EDA Playground [upl. by Pearse935]

System Verilog Tutorial 1 Randomization EDA Playground

Duration: 10:37
19.8K views | Jan 1, 2021

Verilog Tutorial 10 Generate Blocks [upl. by Kalle]

Verilog Tutorial 10 Generate Blocks

Duration: 9:44
26.8K views | Nov 16, 2013

FPGA Programming Projects for Beginners FPGA Concepts [upl. by Etnelav]

FPGA Programming Projects for Beginners FPGA Concepts

Duration: 4:43
107.9K views | Sep 8, 2018

Verilog Programming Series Modulo12 Counter [upl. by Tadashi]

Verilog Programming Series Modulo12 Counter

Duration: 3:43
11.8K views | Nov 28, 2019

4 bit ALU Design in verilog using Xilinx Simulator [upl. by Mairb]

4 bit ALU Design in verilog using Xilinx Simulator

Duration: 13:49
36.5K views | Jan 19, 2018

Verilog Programming Series Finite State Machine [upl. by Llevert641]

Verilog Programming Series Finite State Machine

Duration: 4:20
19.8K views | Dec 13, 2019

How to add a new project in ModelSim [upl. by Ladnik602]

How to add a new project in ModelSim

Duration: 1:15
10.5K views | Jul 18, 2016

System Verilog Tutorial 11 How to use EDA Playground [upl. by Lundeen]

System Verilog Tutorial 11 How to use EDA Playground

Duration: 6:30
11.1K views | May 22, 2021

15 Programming Project Ideas From Beginner to Advanced [upl. by Murvyn559]

15 Programming Project Ideas From Beginner to Advanced

Duration: 16:52
862.7K views | Jan 29, 2021

Verilog Programming Series Dual Port Synchronous RAM [upl. by Patin]

Verilog Programming Series Dual Port Synchronous RAM

Duration: 5:09
18.9K views | Dec 6, 2019

Tutorial 14 Creating a project from scratch in Quartus Prime [upl. by Amimej]

Tutorial 14 Creating a project from scratch in Quartus Prime

Duration: 4:59
64.7K views | Jun 17, 2018

Top 10 FPGA Projects 2019 pantechsolutions fpgaproject [upl. by Violetta]

Top 10 FPGA Projects 2019 pantechsolutions fpgaproject

Duration: 7:47
36.7K views | Oct 10, 2019

Using Multiple Modules in Verilog [upl. by Tamar]

Using Multiple Modules in Verilog

Duration: 14:20
31.5K views | Mar 24, 2020

Visual Stduio Code for Verilog Coding [upl. by Eugeniusz]

Visual Stduio Code for Verilog Coding

Duration: 13:42
63K views | Jun 28, 2018

Lecture 31 MODELING REGISTER BANKS using Verilog by IIT KHARAGPUR [upl. by Ahsirkal638]

Lecture 31 MODELING REGISTER BANKS using Verilog by IIT KHARAGPUR

Duration: 26:47
13.8K views | Oct 7, 2017

Verilog Complete course for beginner level [upl. by Ping]

Verilog Complete course for beginner level

Duration: 2:33:24
10.6K views | Jun 9, 2021

Designing a First In First Out FIFO in Verilog [upl. by Vtehsta]

Designing a First In First Out FIFO in Verilog

Duration: 24:41
30.6K views | May 26, 2020

Verilog Synthesis on EDA Playground 1 of 2 [upl. by Harrad]

Verilog Synthesis on EDA Playground 1 of 2

Duration: 5:27
24.9K views | Nov 24, 2013

26 FPGA Project ➠ ATM Machine Basys 3 FPGA Board Verilog [upl. by Sallyanne]

26 FPGA Project ➠ ATM Machine Basys 3 FPGA Board Verilog

Duration: 31:14
11.9K views | Mar 14, 2021

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